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Espressif Systems /ESP32-S2 /SENS /SAR_MEAS1_CTRL1

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Interpret as SAR_MEAS1_CTRL1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RTC_SARADC_RESET)RTC_SARADC_RESET 0 (RTC_SARADC_CLKGATE_EN)RTC_SARADC_CLKGATE_EN 0FORCE_XPD_AMP 0AMP_RST_FB_FORCE 0AMP_SHORT_REF_FORCE 0AMP_SHORT_REF_GND_FORCE

Description

Configure RTC ADC1 controller

Fields

RTC_SARADC_RESET

SAR ADC software reset.
RTC_SARADC_CLKGATE_EN

Enable bit of SAR ADC clock gate.
FORCE_XPD_AMP
AMP_RST_FB_FORCE
AMP_SHORT_REF_FORCE
AMP_SHORT_REF_GND_FORCE

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data